1. Field of the Invention
The present invention relates, in general, to an electrically erasable, programmable read only memory (hereinafter referred to as "EEPROM") and, more particularly, to an EEPROM with high charge coupling efficiency and program efficiency even at low outer voltage. Also, the present invention is concerned with a simple method for fabricating the EEPROM.
2. Description of the Prior Art
Generally, an EEPROM is known as a semiconductor device capable of electrically writing and erasing data. As for its structure, a floating gate on which charges are accumulated is interposed between a control gate and a gate oxide film.
If a high voltage is applied between the control gate and a drain electrode in the forward direction, high energy electrons generated around the drain electrode are injected over a potential barrier of the thin gate oxide film into the floating gate by not carrier injection. The threshold voltage of transistor varies in accordance with the amount of the injected charges, recording data.
On the other hand, if a high voltage is applied between the control gate and the drain electrode in a backward direction, the electrons injected into the floating gate pass through the tunnel oxide film into the semiconductor substrate, which is called a Fowler-Nordheim tunneling phenomenon, erasing the data recorded in the floating gate.
In such EEPROM, the gate oxide film beneath the floating gate, acting as the tunnel oxide film, is thin enough for the electrons to tunnel while recording and erasing data. In addition, punchthrough voltage and threshold voltage of a transistor should be considered in determining the thickness of the tunnel oxide film.
In order to better understand the background of the present invention a description of conventional techniques will be given below in connection with some drawings.
Referring to FIG. 1, there is shown an example of a conventional EEPROM. As shown in this figure, an oxide film 2 and an island of a floating gate 3 are stacked on a semiconductor substrate 1 in which a drain electrode 4 is formed below the right side of the floating gate 3. And, on the surface of the floating gate 3 and the semiconductor substrate 1 is formed an interlayer insulating film 5 on which a control gate 7 lengthwise extends shielding the floating gate 3. A source electrode 4' is formed in the semiconductor substrate 1 below the left side of the control gate 7 which then serves as a selecting gate between the floating gate 3 and the source electrode 4'.
Such a conventional EEPROM is superior in charge coupling efficiency by virtue of the control gate's shielding the floating gate. However, it is disadvantageous in that the two distinct ion implantation processes should be effected in order to form the drain electrode and the source electrode in respective areas of the semiconductor substrate.
Turning to FIG. 2, there is another example of a conventional EEPROM. Shown is a split gate type EEPROM wherein an oxide film 12 and an island of a floating gate 13 are stacked on a semiconductor substrate 11. An interlayer insulating film 15 is formed on the entire surface of the floating gate 13 and the exposed semiconductor substrate 11. A control gate 17 on the interlayer insulating film extends from the upper surface of the floating gate 13 to a predetermined portion of the semiconductor substrate 11. While a drain electrode 14 is formed below the right side of the floating gate 13, a source electrode 14' is formed below the left side of the control gate 17. It serves as a selecting gate between the floating gate 13 and the source electrode 14'.
A significant disadvantage of the split gate type EEPROM is that one side wall of the floating gate does not overlap with the control gate, so that the charge coupling ratio is lowered, which results in a decrease of program efficiency.